Programmable logic devices (PLDs) typically include a plurality of logic elements and associated interconnect resources that are programmed by a user to implement user-defined logic operations (that is, a user's circuit). PLDs are programmed using a personal computer or workstation, appropriate software and in some cases a device programmer. Therefore, unlike application specific integrated circuits (ASICs) that require a protracted layout process and an expensive fabrication process to implement a user's logic operation, a PLD may be utilized to implement the logic operation in a relatively quick and inexpensive manner.
FIG. 1(A) is a simplified diagram showing a basic Field Programmable Gate Array (FPGA) 100, which is a type of PLD. FPGA 100 includes an array of configurable logic blocks (CLBs) CLB-1,1 through CLB-4,4 that are surrounded by input/output blocks (IOBs) IOB-1 through IOB-16, and programmable interconnect resources that include vertical interconnect wiring segments 120 and horizontal interconnect wiring segments 121 extending between the rows and columns of CLBs and IOBS. Each CLB includes configurable combinational circuitry and optional output registers that are programmed to implement a portion of a user's logic function. The interconnect wiring segments of the programmable interconnect resources are configured using various switches to generate signal paths between the CLBs that link the logic function portions. Each IOB is similarly configured to selectively utilize an associated pin (not shown) of FPGA 100 either as a device input pin, a device output pin, or a bi-directional pin. Although greatly simplified, FPGA 100 is generally consistent with FPGAs that are produced, for example, by Xilinx, Inc. of San Jose, Calif.
FIGS. 1(B) through 1(D) are simplified diagrams showing examples of the various switches associated with the programmable interconnect resources of FPGA 100. FIG. 1(B) shows an example of a six-way segment-to-segment switch 122 that selectively connects vertical wiring segments 120(1) and 120(2) and horizontal wiring segments 121(1) and 121(2) in accordance with configuration data stored in memory cells M1 through M6. Alternatively, if horizontal and vertical wiring segments 120 and 121 do not break at an intersection, a single transistor makes the connection. FIG. 1(C) shows an example of a segment-to-CLB/IOB input switch 123 that selectively connects an input wire 110(1) of a CLB (or IOB) to one or more interconnect wiring segments in accordance with configuration data stored in memory cells M7 and M8. FIG. 1(D) shows an example of a CLB/IOB-to-segment output switch 124 that selectively connects an output wire 115(1) of a CLB (or IOB) to one or more interconnect wiring segments in accordance with configuration data stored in memory cells M9 through M11.
Signal Contention Problem
FIG. 2(A) is a simplified schematic showing one row of CLBs of FPGA 100 (see FIG. 1(A)). As indicated in FIG. 2(A), CLB-1,1 is programmably connected to wiring segment 121(1) via CLB-to-segment output switch 124(1), and CLB-1,2 is programmably connected to wiring segment 121(2) via CLB-to-segment output switch 124(2). Wiring segments 121(1) and 121(2) are programmably connected via segment-to-segment switch 122(1).
When power is initially applied to a typical PLD (referred to below as "power-up"), the configuration memory cells of the PLD "wake up" in random states. These random states sometimes cause the configurable logic circuits (e.g., IOBs and CLBs) to transmit opposing (i.e., high and low voltage) signals onto the wiring segments of the interconnect resources. A signal contention problem occurs when the sources of these opposing signals are linked through the interconnect resources, thereby potentially damaging and/or locking-up the PLD.
FIG. 2(B) shows a relevant portion of the CLB row of FIG. 2(A), and illustrates an example of a power-up signal contention problem between CLB-1,1 and CLB-1,2 (see FIG. 2(A)). The present example assumes that the internal circuitry of CLB-1,1 "wakes up" in a state that transmits a high (VDD) output signal to CLB-to-segment output switch 124(1). Conversely, the internal circuitry of CLB-1,2 "wakes up" in a state that transmits a low (GND) output signal to CLB-to-segment output switch 124(2). In addition, the present example assumes that memory cells M11 of CLB-to-segment output switches 124(1) and 124(2) "wake up" to pass these high and low signals to wiring segments 121(1) and 121(2), respectively. Finally, the present example assumes that memory cell M6 of segment-to-segment switch 122(1) "wakes up" in a state that turns on its associated pass transistor to connect wiring segments 121(1) and 121(2). Based on the "wake up" states provided above, signal contention is generated between VDD CLB-1,1 and GND CLB-1,2 that can potentially damage and/or create unacceptably high current in FPGA 100.
Signal contention can also occur after device power-up in PLDs that support reconfiguration. Reconfiguration typically includes deactivation of the PLD (which operates according to "old" configuration data), writing "new" reconfiguration data into the configuration memory, and then re-activating the PLD such that it operates according to the "new" configuration data. Signal contention can occur during this reconfiguration process while the "new" configuration data is being written into the configuration memory. Specifically, signal contention can occur while the configuration memory contains some "old" configuration data and some "new" configuration data (i.e., while the new configuration data is being written into configuration memory). For example, referring to FIG. 2(B), assume the "old" configuration data causes CLB-1,1 to transmit a high (VDD) output signal to CLB-to-segment output switch 124(1), causes CLB-to-segment output switch 124(1) to pass this high signal to wiring segment 121(1), and causes segment-to-segment switch 122(1) to connect wiring segments 121(1) and 121(2). If this "old" configuration data is still stored in the configuration memory when "new" configuration data is written that causes CLB-to-segment output switch 124(2) to transmit a low (GND) output signal from CLB-1,2 to interconnect wiring segment 121(2), then signal contention is generated between VDD CLB-1,1 and GND CLB-1,2 that can potentially damage and/or create unacceptably high current in FPGA 100.
A well-known mechanism for preventing signal contention at device power-up is to fabricate a PLD using asymmetric transistors that are biased to "wake up" in a known state. However, such asymmetric transistors are unreliable, and also require significantly more area than symmetric transistors.
Crowbar Current Problem
FIG. 2(C) is a simplified schematic showing another portion of FPGA 100 of FIG. 1(A), and illustrates an example of how buffers utilized in the interconnect resources of some PLDs can create a significant crowbar current problem. FIG. 2(C) shows a portion of the interconnect resources of FPGA 100 including interconnect wiring segments 121(3) and 121(4) that are programmably connected by a pass transistor 210 of segment-to-segment switch 122(2), and a buffer circuit 220 that is connected between interconnect wiring segment 121(4) and an input terminal of CLB-X,Y. Buffer circuit 220 includes a CMOS inverter 225 having a P-channel transistor P1 and an N-channel transistor N1, each having a gate terminal connected to interconnect wiring segment 121(4). During operation of FPGA 100, logic signals (e.g., VDD or ground) are transmitted from interconnect wiring segment 121(3) onto interconnect wiring segment 121(4) via pass transistor 210 when configuration memory cell M6 transmits a high voltage to the gate terminal of pass transistor 210.
A "crowbar current" (also called a "short-circuit current") is the current that flows from a P-channel transistor to an N-channel transistor while the input signal driving both transistors is at an intermediate voltage (i.e., both transistors are partially on). A crowbar current undesirably consumes extra power and does not contribute to charging the output node. A crowbar current is generated in buffer 220 during operation of FPGA 100 that is due to the voltage drop across the pass transistors of the interconnect resources. As shown in FIG. 2(C), when a high (VDD) voltage level is transmitted on interconnect wiring segment 121(3) that is passed by pass transistor 210 to interconnect wiring segment 121(4), the voltage level on interconnect wiring segment 121(4) (VDD-VTH) is one N-channel transistor threshold voltage (i.e., one VTH) lower than the voltage level on interconnect wiring segment 121(3). Because the voltage applied to the gate terminal of P-channel transistor P1 of inverter 225 is less than VDD, a crowbar current is generated in buffer 220. The cumulative effect of the crowbar current from all buffers of FPGA 100 can be very significant.
To prevent crowbar current from buffer 220, a feedback pull-up P-channel transistor P2 is utilized to pull up the input of inverter 225 to VDD (i.e., when a high voltage level is transmitted on interconnect wiring segment 121(3)). Pull-up transistor P2 is connected between VDD and the input terminal of inverter 225, and has a gate terminal connected to the output terminal of inverter 225. When a high voltage signal is applied to the input terminal of inverter 225, the output terminal is pulled low by N-channel transistor N1. This low voltage level at the output terminal turns on pull-up P-channel transistor P2, thereby pulling up the input terminal to VDD. Therefore, crowbar current through P-channel transistor P1 is prevented by pull-up transistor P2 because the voltage level applied to the gate terminal of transistor P1 is VDD.
Although pull-up P-channel transistor P2 prevents crowbar current from active buffers, it may not prevent crowbar current that occurs in buffers connected to unused interconnect wiring segments of FPGA 100. Referring again to FIG. 2(C), assume that interconnect wiring segment 121(4) is not utilized by a user's logic function. Therefore, during operation of FPGA 100, no logic signals are passed to interconnect wiring segment 121(4), thereby allowing it to float between ground and the system voltage. This intermediate (floating) voltage on interconnect wiring segment 121(4) is applied to inverter 225. Because the voltage level at the input terminal of inverter 225 is neither high nor low, both N-channel transistor N1 and P-channel transistor P1 are partially turned on. The voltage level at the output terminal may be insufficient to sufficiently turn on pull-up transistor P2. Therefore, a crowbar current can be generated through P-channel transistor P1 in every unused buffer of FPGA that is connected to a floating interconnect wiring segment.
In conventional PLDs, the floating interconnect wire problem is addressed by "tying" all unused interconnect wiring segments to a common voltage source. This "tying" process is performed by determining a supplemental routing solution (i.e., in additional to the routing solution needed to implement the user's logic function). In one embodiment, the supplemental routing solution is used to connect all unused interconnect wires to VDD, thereby fully turning off P-channel transistor P1 (and fully turning on N-channel transistor N1 and pull-up transistor P2) in all buffers connected to the unused interconnect wiring segments.
A problem with the "tying" process is that it is very time-consuming to generate the supplemental routing solution, thereby increasing the time required to program a PLD. Further, it is not always possible to generate a supplemental solution that ties all unused interconnect wires to VDD (i.e., some inaccessible interconnect wires are left floating). Moreover, the "tying" process does not address signal contention at device power-up.
Low Voltage Threshold Transistors
While PLDs provide numerous advantages over application specific integrated circuits (ASICs), signal propagation through the general interconnect resources of PLDs is typically slower than through the dedicated hard-wired connections found in an ASIC. Therefore, PLD manufacturers strive to utilize the most advanced fabrication technologies available to provide the fastest possible products.
Recent fabrication technology advances have provided low threshold voltage (low V.sub.th), high-speed transistors. Low V.sub.th transistors are fabricated by altering the semiconductor process parameters (e.g., by altering the amount of diffused dopant) in accordance with known techniques.
A problem with low V.sub.th transistors is that they tend to leak excessively when, in the case of N-channel transistors, they are turned off (i.e., 0 volts is applied to the gate terminal). This characteristic makes low V.sub.th transistors poorly suited for PLDs because numerous pass gates remain turned off (e.g., throughout the interconnect resources of FPGA 100, described above) when the PLD is programmed to implement a user's logic function.
Therefore, what is needed is a method for overcoming the start-up contention problems of conventional FPGAs, described above. What is also needed is a method/circuit that minimizes crowbar current and leakage both from used and from unused interconnect resources of the PLD without the need to generate a supplemental routing solution. Further, what is needed is a method/circuit that supports the efficient use of low V.sub.th transistors in PLDs.